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MPEG-4 SP Codec Product Specification

Part Number:

Mainstream™ MPEG-4 SP Codec

Short Description:

MPEG-4 Combined Encoder and Decoder

Portability:

ASIC, FPGA

ASIC Target:

0.13, 0.18, 0.25

FPGA Target:

Altera, Xilinx

Type:

Soft

Compliant Standard:

ISO 14496-2 (MPEG-4)

Maturity:

Silicon verified

Availability:

Now

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Overview :

IndigoVision’s Mainstream™ MPEG-4 silicon-verified video codec IP adds high-performance duplex MPEG-4 video encoding and decoding, as a single combined module, to existing systems. It is particularly suited to adding both video encoding and playback capabilities to cameras, set-top boxes, MP3 players and other portable, battery-powered devices, such as mobile phones and PDAs.

The Mainstream™ MPEG-4 video codec is fully compliant with the MPEG-4 Simple Profile standard. The Mainstream™ IP also contains support for some Advanced Simple Profile (ASP) tools for higher performance and can encode and decode arbitrary resolutions up to full ASP Level 5 (D1/DVD) resolutions, all at full frame rate.

Based on the single clocked, synchronous, fully hardware pipelined Mainstream™ architecture the codec requires minimal intervention from a host processor and can be controlled by a low-cost, low-power processor such as in an ARM or MIPS based SOC. Further, both the encoder and decoder have been combined into a single module for a reduced footprint but maintain the ability to perform duplex operation, such as simultaneous compression and live playback.

Features :

  • MPEG-4 Video Codec

    • Fully compliant ISO 14496-2 MPEG-4 Simple Profile L0, L1, L2, L3

    • Compliant Advanced Simple Profile tools

    • Advanced Simple Profile Levels L0 through L5

    • Baseline ITU-T H.263 compliant

    • Arbitrary resolutions up to 720x576/480 pixels at 25/30fps

    • Encodes and decodes bitstreams up to 12Mbps

    • Full duplex operation (dependent on clock speed)

    • Real-time multi-pass encoding (dependent on clock speed)

    • Multi-rate encoding (dependent on clock speed)

    • Multi-decode for multi-stream rendering (dependent on clock speed)

    • Error resilience including slice resynchronization

 

 

Benefits:

  • Easy Integration

    • Negligible processing from host

    • Low power operation

      • <5mW for CIF encode at 30fps

    • Software bit-accurate models

    • Interfaces available

      • Simple DMA based

      • AMBA

    • Requires only a single low-cost external SDRAM device

    • Support technology available

      • Video display generator (CCIR-656 video output)

      • Video capture (CCIR-656 video input)

  • Advanced Compression

    • I-VOP, and P-VOP frames

    • AC/DC prediction

    • Method 1 and 2 MPEG-4 quantisation

    • Advanced noise reduction spatial pre-filtering for improved coding efficiency

    • Motion estimation: +/-16 pel search range using log search

    • Support for ½-pel motion estimation

    • True edge preservation

    • Variable bitrate control

    • Inbuilt intra-frame constant bitrate in hardware

    • Inter-frame constant bitrate control in software e.g. MPEG-4 Annex L

    • Video packets with optional HEC

    • Unrestricted motion vector support (decoder only)

    • Four motion vector prediction (decoder only)

    • Data partitioning and RVLC (decoder only using software)

  • Flexibility

    • Frame-based control

    • Programmable Method 1 quantisation tables

    • Encoder statistics including distortion and frame MAD for advanced rate control

    • Configurable pre-processing filter strengths

    • Programmable motion vector bias

    • VTI control

    • Programmable forced update control

    • Definable inter/intra decision thresholds

 

UMC Rating:

Gold: 0.25um

FPGA Technology:

Altera: Stratix
Xilinx: Virtex-II Pro


 

 

 
































































 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 









   
 

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