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MPEG-4 SP Codec Product Specification
Part Number: |
Mainstream™ MPEG-4 SP Codec |
Short Description: |
MPEG-4 Combined Encoder and Decoder |
Portability: |
ASIC, FPGA |
ASIC Target: |
0.13, 0.18, 0.25 |
FPGA Target: |
Altera, Xilinx |
Type: |
Soft |
Compliant Standard: |
ISO 14496-2 (MPEG-4) |
Maturity: |
Silicon verified |
Availability: |
Now |
for
a PDF version of this page
Overview :
IndigoVision’s Mainstream™ MPEG-4 silicon-verified video codec IP adds high-performance duplex MPEG-4 video encoding and decoding, as a single combined module, to existing systems. It is particularly suited to adding both video encoding and playback capabilities to cameras, set-top boxes, MP3 players and other portable, battery-powered devices, such as mobile phones and PDAs.
The Mainstream™ MPEG-4 video codec is fully compliant with the MPEG-4 Simple Profile standard. The Mainstream™ IP also contains support for some Advanced Simple Profile (ASP) tools for higher performance and can encode and decode arbitrary resolutions up to full ASP Level 5 (D1/DVD) resolutions, all at full frame rate.
Based on the single clocked, synchronous, fully hardware pipelined Mainstream™ architecture the codec requires minimal intervention from a host processor and can be controlled by a low-cost, low-power processor such as in an ARM or MIPS based SOC. Further, both the encoder and decoder have been combined into a single module for a reduced footprint but maintain the ability to perform duplex operation, such as simultaneous compression and live playback.
Features :
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Fully compliant ISO 14496-2 MPEG-4 Simple Profile L0, L1, L2, L3
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Compliant Advanced Simple Profile tools
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Advanced Simple Profile Levels L0 through L5
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Baseline ITU-T H.263 compliant
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Arbitrary resolutions up to 720x576/480 pixels at 25/30fps
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Encodes and decodes bitstreams up to 12Mbps
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Full duplex operation (dependent on clock speed)
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Real-time multi-pass encoding (dependent on clock speed)
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Multi-rate encoding (dependent on clock speed)
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Multi-decode for multi-stream rendering (dependent on clock speed)
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Error resilience including slice resynchronization
Benefits:
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Negligible processing from host
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Low power operation
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Software bit-accurate models
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Interfaces available
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Requires only a single low-cost external SDRAM device
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Support technology available
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Advanced Compression
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I-VOP, and P-VOP frames
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AC/DC prediction
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Method 1 and 2 MPEG-4 quantisation
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Advanced noise reduction spatial pre-filtering for improved coding efficiency
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Motion estimation: +/-16 pel search range using log search
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Support for ½-pel motion estimation
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True edge preservation
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Variable bitrate control
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Inbuilt intra-frame constant bitrate in hardware
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Inter-frame constant bitrate control in software e.g. MPEG-4 Annex L
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Video packets with optional HEC
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Unrestricted motion vector support (decoder only)
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Four motion vector prediction (decoder only)
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Data partitioning and RVLC (decoder only using software)
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Flexibility
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Frame-based control
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Programmable Method 1 quantisation tables
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Encoder statistics including distortion and frame MAD for advanced rate control
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Configurable pre-processing filter strengths
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Programmable motion vector bias
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VTI control
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Programmable forced update control
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Definable inter/intra decision thresholds
UMC Rating: |
Gold: 0.25um |
FPGA Technology: |
Altera: Stratix
Xilinx: Virtex-II Pro
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