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MPEG-4 SP Hardware Decoder Product Specification

Part Number:

Mainstream™ MPEG-4 SP Decoder

Short Description:

MPEG-4 Simple Profile Decoder

Portability:

ASIC, FPGA

ASIC Target:

0.13, 0.18, 0.25

FPGA Target:

Altera, Xilinx

Type:

Soft

Compliant Standard:

ISO 14496-2 (MPEG-4)

Maturity:

Silicon verified

Availability:

Now

for a PDF version of this page

Overview:

IndigoVision’s Mainstream™ MPEG-4 silicon-verified video decoder IP adds high-performance MPEG-4 video decoding to existing systems. It is particularly suited to adding playback capabilities to cameras, set-top boxes, MP3 players and other portable, battery-powered devices, such as mobile phones and PDAs.

The Mainstream™ MPEG-4 video decoder is fully compliant with the MPEG-4 Simple Profile standard. The Mainstream™ IP also contains support for some Advanced Simple Profile (ASP) tools for higher interoperability and can decode arbitrary resolutions up to full ASP Level 5 (D1/DVD) resolutions, all at full frame rate.

Based on the single clocked, synchronous, fully hardware pipelined Mainstream™ architecture the decoder requires minimal intervention from a host processor and can be controlled by a low-cost, low-power processor such as in an ARM or MIPS based SOC. The decoder is provided as a reduced footprint standalone module for decode-only applications, or where separate encoders and decoders are the preferred solution.

Features:

  • MPEG-4 Video Decoder

    • Fully compliant ISO 14496-2 MPEG-4 Simple Profile L0, L1, L2, L3

    • Compliant Advanced Simple Profile tools

    • Advanced Simple Profile Levels L0 through L5

    • Baseline ITU-T H.263 compliant

    • Arbitrary resolutions up to 720x576/480 pixels at 25/30fps

    • Decodes bitstreams up to 12Mbps

    • Multi-decode for multi-stream rendering (dependent on clock speed)

    • Error resilience including slice resynchronization

    • Decodes completely from Video Object Plane (VOP) entry point

Benefits:

  • Easy Integration

    • Negligible processing from host

    • Low power operation

      • <5mW for CIF decode at 30fps

    • Software bit-accurate decoder model

    • Interfaces available

      • Simple DMA based

      • AMBA

    • Requires only a single low-cost external SDRAM device

    • Support technology available

      • Video display generator (CCIR-656 video output)

  • Advanced Decompression

    • I-VOP, and P-VOP frames

    • AC/DC prediction

    • Method 1 and 2 MPEG-4 quantisation

    • Video packets with optional HEC

    • Unrestricted motion vector support

    • Four motion vector prediction

    • Data partitioning and RVLC (software-only)

  • Flexibility

    • Frame-based control

    • Programmable Method 1 quantisation tables

UMC Rating:

Gold: 0.25um

FPGA Technology:

Altera: Stratix
Xilinx: Virtex-II Pro

 

 

 
































































 

 

 


   
 

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